Time-division multiplex is the transmission of information from several signal channel subsystems through one communication bus with different channel samples staggered in time to form a composite pulse train. A remote terminal or module is the name commonly given the electronics necessary to provide an interface between the bus and a subsystem. A bus controller is the electronics that serve the function of commanding, scanning and monitoring "bus traffic" to prevent overlap and erroneous communications.
The electronic battlefield of the future represents an environment in which vast amounts of data from a multitude of sources requires processing. Mission success and combat effectiveness of weapon systems depends on the ability to distribute and process data within limited space constraints.
Today's combat vehicles have a centralized power distribution system which occupies a large volume and, consequently, limits the space for electronic enhancements to the vehicle. The centralized nature of the conventional system results in large distribution boxes and long cable runs that increase the system's weight, size, cost and vulnerability. Conventional point-to-point discrete wiring approaches result in severe limitations to the continued expansion of electronic and electrical equipment. This problem applies to both signal and power circuits.
Consequently, instead of one centralized distribution center, there is a need for a single interface chip device which can be placed at intermediate locations in remote modules to control power and/or collect and distribute information to eliminate the need to discretely wire remote locations directly to the distribution center.
The U.S. Pat. No. 4,136,400 to Caswell et al. discloses a microprocessor-based CMOS chip which has a bus controller mode and a remote terminal mode and which operates in a time-division multiplex serial data bus system. The chip is capable of satisfying the performance requirements of military standard 1553A which relates to serial data bus systems. A data format encoder and data format decoder provide means to convert from Manchester bi-phase data to NRZ data for receiving data from the data bus and to make the opposite conversion for transmitting data over the data bus.
The Caswell chip is a programmable chip that can (along with a Control ROM and Subsystem) implement the MIL-STD-1553 requirement for serial data bus communications. The device does not contain any logic that would allow it to directly interface with I/O devices. The device requires a processor, memory, software, and subsystem hardware if it were to interface to switches, sensors, A-to-D converters, etc.
Protocol interpretation as provided by the Caswell patent is handled by the external ROM and a subsystem coupled to the chip. A microprocessor is required in the subsystem hardware to utilize the data from the data terminal chip. This is possible since military standard 1553A is directly used to interconnect several complex microprocessor-based subsystems within a military aircraft.
The U.S. Pat. No. 4,471,489 to Konetski discloses an electronic circuit which automatically switches a telephone modem to a receive or transmit mode. Modems are used in data communication systems to transfer data between two or more computers. The circuit has no capability to interface with anything other than standard computer interfaces such as RS-232.
The U.S. Pat. No. 4,453,229 to Schaire discloses a bus interface unit capable of handling the protocol of a wide variety of flexible bus communication message formats and data transfer algorithms. The unit is capable of operating in either a bus controller or a terminal mode. In the bus controller mode, the unit initiates inner subsystem messages. In the remote terminal mode, the unit responds in a predetermined manner to commands from another similar unit acting as a bus controller.
The U.S. Pat. No. 4,794,525 to Pickert et al. discloses external interface control circuitry which couples a microcomputer system to an external device. The control circuitry includes a microcomputer or power switch for supplying power to the external device in response to a PSC signal and bus control for gating interface signals from the microcomputer with a PD signal for application to the external device.
The U.S. Pat. No. 4,547,880 to DeVita discloses a communication control apparatus for interconnecting a large number of user terminals, main frame computer system, microcomputers, remote digital devices and the like using some of the concepts inherent in statistical multiplexers, intelligent switches and local area network devices implemented in a relatively compact configuration.
The U.S. Pat. No. 4,554,657 to Wilson discloses a multiplex bus including a bus controller for controlling the traffic on a multiplex bus network. The bus controller can address a remote control terminal to activate one of a plurality of extended buses and then address the remote terminals thereon.
Motorola data sheet for the MC68561 describes a multi-protocol communications controller (MPCC) which interfaces a single serial communications channel to an MC68008/MC6800 microcomputer-based system. The device is used to send data from one microprocessor to another microprocessor. The device does not have a means to directly interface to input-output devices.
The U.S. Pat. No. 4,331,835 to Gueldner et al. discloses an interface unit for modular telecommunication systems. Data transfer across an interlink bus is performed under control of an interlink bus controller. Data characters are transmitted in time multiplex mode. A receiving unit stores data in a buffer memory immediately before translating the same to an associated switching block.
Other U.S. prior art patents of a more general interest include U.S. Pat. Nos. 3,978,454, 4,137,565, 4,245,301, 4,287,563, 4,344,127, 4,371,932, 4,451,881 and 4,507,781.
A typical prior art bus controller includes a microprocessor along with specific application software to perform the bus control functions. The processor and software determine when data is to be transmitted and what to do with particular data that is received. Bus interface logic is in control of getting data from one location to another when told to by the microprocessor. The BUS interface logic consists of serial bus drivers/receivers, encoders/decoders, data error detection (parity checks), and data storage. The Bus interface hardware must be capable of receiving and storing data from the processor prior to transmission. It must also store data received from the serial bus and make it available to the processor.
A typical bus operates in the remote mode much the same way that it does in the bus controller mode. The Bus interface logic receives the serial data and converts it into parallel data. In some systems (i.e. Motorola MC68561) this data would simply be made available to a local microprocessor and application software. The Bus Interface would wait to be told what to do next.
In other systems, such as the Caswell chip, the received data may be interpreted by the Bus interface logic and then loaded in external dual port memory. Depending on the type of message received the Bus interface logic could respond with an echo which contains data from a location within the external memory. The data in this memory would be placed there or read by a local microprocessor running application software. Depending on the data received and the application software, the microprocessor could instruct the remote node's support hardware to perform an input or output function. After processing the results of this input or output function the processor could place new data in the dual port memory. In any case, the subsystem in a typical command response communications system must have a microprocessor and memory to make any use of the data received from the serial bus. In other words, the Motorola and Caswell devices essentially just control data communications between multiple microprocessors.